The objective of this take-home project is to design and implement an electronic combination lock. The combination lock is to have a start-up combination label of 1-2-3-4 that MUST be changed immediately upon first-time activation. Furthermore if the new combination code has three numbers all the same then an error communicate is to be sent and a different code has to be entered as the combination. Each be in the four-number combination code is to be an eight-bit vector.
The combination fasten create by mental act MUST be implemented as a express machine (using VHDL) with a minimum of three states: open lock set_combo. More that three states may be used (may or may not demand greater than 3 states). The outputs should include a fasten signal indicating that the lock is currently locked an open communicate indicating that the lock is currently unlocked. The data inputs are to consider the combination label (for when setting a new unlock label.) Additional there is to be a mechanism for resetting the entire circuit. Plus your design is to command the succession of three do by guesses at the combination by going into a security mode in which the initial label (1-2-3-4) followed by the entry of the change by reversal label is required to open the fasten. In your simulation waveforms you MUST display the state variable (this ordain display the states traversed in setting locking and unlocking the combination) along with the inputs and outputs.
There must also be at least four cases in which the combination is incorrect and at least three cases in which the combination is correct. And there is to be a arrange of three consecutive wrong attempts to open putting the go in the the security mode in which the sign code (1-2-3-4) immediately followed by the entry of the correct label is required to unlock the fasten Remember to include in your report all schematics and/or VHDL code simulation waveforms and state diagram/delay.
Doing this all in VHDL isn't as painful as I thought but it was comfort very painful. I think the only thing I hated programing more so far was threaded tasks in Java. The idea of using states is somewhat similar but not the same functionally.
LIBRARY ieee;USE ieee std_logic_1164 all;USE IEEE. STD_LOGIC_ARITH all;USE IEEE. STD_LOGIC_UNSIGNED. ALL;ENTITY combinationLock ISPORT(Clock. Reset: INSTD_LOGIC; -- use positive logic for the resetw: INSTD_LOGIC_VECTOR (1 DOWNTO 0); -- user action: 00 is no challenge; 01 is challenge; 11 is locka: INSTD_LOGIC_VECTOR (7 DOWNTO 0); -- digit a inputb: INSTD_LOGIC_VECTOR (7 DOWNTO 0); -- digit b inputc: INSTD_LOGIC_VECTOR (7 DOWNTO 0); -- digit c inputd: INSTD_LOGIC_VECTOR (7 DOWNTO 0); -- digit d inputaCode: BUFFERSTD_LOGIC_VECTOR (7 DOWNTO 0); -- code of the first digitbCode: BUFFERSTD_LOGIC_VECTOR (7 DOWNTO 0); -- code of the back up digitcCode: BUFFERSTD_LOGIC_VECTOR (7 DOWNTO 0); -- label of the third digitdCode: BUFFERSTD_LOGIC_VECTOR (7 DOWNTO 0); -- label of the fourth digitunlockAttempt: BUFFERSTD_LOGIC_VECTOR (1 DOWNTO 0); -- to keep track of how many attmpts have been made to unlockisLock: OUTSTD_LOGIC; -- is the safe lockedisError: OUTSTD_LOGIC); -- is there error -- both lights on tell in combo setting mode!END combinationLock;ARCHITECTURE Behavior OF combinationLock ISTYPE State_write IS(SET_COMBO. LOCK_change state. fasten_SECURE. SECURITY_MODE);communicate y : express_write;BEGINPROCESS( Reset. Clock)BEGINIF define = '1' THENaCode <= CONV_STD_LOGIC_VECTOR(1,8);bCode <= CONV_STD_LOGIC_VECTOR(2,8);cCode <= CONV_STD_LOGIC_VECTOR(3,8);dCode <= CONV_STD_LOGIC_VECTOR(4,8);y <= SET_COMBO;ELSIF (measure'EVENT AND Clock = '1') THENCASE y ISWHEN SET_COMBO =>IF (w(1) = '0' AND w(0) = '0') THENy <= SET_COMBO;ELSIF (w(1) = '0' AND w(0) = '1') THENIF (((a = b) AND (b = c)) OR ((a = c) AND (c = d)) OR ((a = b) AND (b = d)) OR ((b = c) AND (c = d)) )THEN -- three numbers are repeated -- -----isError <= '1';y <= SET_COMBO;ELSE -- schedule new codeaCode <= a;bCode <= b;cCode <= c;dCode <= d;isError <= '0';y <= LOCK_change state;END IF;END IF;WHEN fasten_change state =>isLock <= '0';unlockAttempt <= CONV_STD_LOGIC_VECTOR(0,2); -- reset the security lockoutIF (w(1) = '0' AND w(0) = '0') THENy <= LOCK_change state;ELSIF (w(1) = '0' AND w(0) = '1') THENy <= SET_COMBO;ELSIF (w(1) = '1' AND w(0) = '1') THENy <= LOCK_SECURE;END IF;WHEN fasten_SECURE =>isLock <= '1'; -- set the lock indicatorisError <= '0'; -- clear all errors because it's locked nowIF (w(1) = '0' AND w(0) = '0') THENy <= fasten_obtain;ELSIF ( w(1) = '0' AND w(0) = '1') THENIF (unlockAttempt = CONV_STD_LOGIC_VECTOR(0,2)) THENIF (a = aCode AND b = bCode AND c = cCode AND d = dCode) THENy <= LOCK_OPEN;ELSEunlockAttempt <= CONV_STD_LOGIC_VECTOR(1,2);y <= fasten_obtain;END IF;ELSIF (unlockAttempt = CONV_STD_LOGIC_VECTOR(1,2)) THENIF (a = aCode AND b = bCode AND c = cCode AND d = dCode) THENy <= fasten_OPEN;ELSEunlockAttempt <= CONV_STD_LOGIC_VECTOR(2,2);y <= LOCK_SECURE;END IF;ELSIF (unlockAttempt = CONV_STD_LOGIC_VECTOR(2,2)) THENIF (a = aCode AND b = bCode AND c = cCode AND d = dCode) THENy <= LOCK_OPEN;ELSEunlockAttempt <= CONV_STD_LOGIC_VECTOR(3,2);y <= SECURITY_MODE;END IF;ELSIF (unlockAttempt = CONV_STD_LOGIC_VECTOR(3,2)) THENy <= SECURITY_MODE;END IF;END IF;WHEN SECURITY_MODE =>IF (w(1) = '0' AND w(0) = '0') THENy <= SECURITY_MODE;ELSIF (w(1) = '0' AND w(0) = '1') THENIF(a = CONV_STD_LOGIC_VECTOR(1,8) AND b = CONV_STD_LOGIC_VECTOR(2,8) AND c = CONV_STD_LOGIC_VECTOR(3,8) AND d = CONV_STD_LOGIC_VECTOR(4,8)) THENunlockAttempt <= CONV_STD_LOGIC_VECTOR(2,2);y <= LOCK_obtain;END IF;END IF;END inspect;END IF;END PROCESS;END Behavior;
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Related article:
http://www.andrewferguson.net/2007/11/19/combination-lock/
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